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HA16178P/FP
Power Factor Correction Controller IC
REJ03D0903-0100 Rev.1.00 Jun 12, 2007
Description
The HA16178P/FP is a power-factor correction (PFC) controller IC. This IC adopts continuous conduction mode as PFC operation. Various functions such as over voltage detection, over current detection, soft start, feedback-loop disconnection detection, are incorporated in a single chip. This eliminates a significant amount of external circuitry. PFC operation can be turned on and off by an external control signal. By using this function, PFC operation can be disabled at low input voltage, allowing remote control from the secondary side. A soft-start control pin provides for the easy adjustment of soft-start operation, and can be used to prevent overshooting of the output voltage.
Features
* Maximum ratings Power-supply voltage Vcc: 24 V Operating junction temperature Tjopr: -40 to 125C * Electrical characteristics VREF output voltage VREF: 5.0 V 3% UVLO operation start voltage VH: 10.5 0.7 V UVLO operation stop voltage VL: 9.0 0.5 V PFC output maximum ON duty Dmax-out: 95% (typ.) * Functions Continuous conduction mode Over voltage detection Over current detection Soft start Feedback loop disconnection detection PFC function on/off control Package lineup: SOP-16 and DILP-16
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 1 of 24
HA16178P/FP
Pin Arrangement
OUT 1 PGND 2 SGND 3 NC 4 PFC-ON 5 VREF 6 CAO 7 CS 8 (Top view) 16 VCC 15 SS 14 EO 13 FB 12 IAC 11 NC 10 CT 9 RT
Pin Description
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin Name OUT PGND SGND NC PFC-ON VREF CAO CS RT CT NC IAC FB EO SS VCC I/O Output -- -- -- Input Output Output Input/Output Input/Output Output -- Input Input Output Output Input Function Power MOS FET gate driver output Ground Ground No connection PFC function on/off signal input Reference voltage output Current control error amplifier output Current sense signal input Timing resistor for operational frequency adjust Timing capacitor for operational frequency adjust No connection Multiplier reference current input Voltage control error amplifier input Voltage control error amplifier output Timing capacitor for soft start time adjust Power supply voltage input
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 2 of 24
HA16178P/FP
Block Diagram
VCC
16
5 V Internal Bias
H
10.5 V UVLO
VREF
5 V VREF Generator
27.5 V
L
6
VREF In GOOD Out VREF GOOD
9.0 V
RT 9 CT 10
CAO
770 ns 15.4 s 0.65 V 3.6 V
PFC-DT RAMP UVL
65 kHz
R S
Q Q
Gate Driver 1.0 A (PEAK)
1
OUT
Oscillator 7
VREF
SS
R S
Q Q
IMO = K x {IAC x (VEO - 1 V)}
IAC
CAMP
12
IAC
VE O
IMO
VREF
K
55 k 3.3 k
CS
CLIMIT
8
Gain Select
K = 0.20
-0.30 V
EO
Gain Selector
K = 0.05
14
2.5 V
VREF
FB
13
VAMP
2.688 V 2.638 V
B+OVP 25 A
15 SS
PGND
0.50 V
PFC-ON 5
0.1
2
FB LOW PFC-OFF
SGND
1.75 V 1.60 V
3
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 3 of 24
HA16178P/FP
Absolute Maximum Ratings
(Ta = 25C)
Item Supply voltage OUT peak current OUT DC current Terminal voltage CAO voltage EO voltage PFC-ON voltage PFC-ON clamp current RT current CT current IAC current CS voltage VREF current Power dissipation Operating junction temperature Storage temperature Notes: 1. 2. 3. 4. VCC Ipk-out Idc-out Vi-group1 Vi-group2 Vcao Veo Vpfc-on Ipfc-on-clamp Irt Ict Iiac Vi-cs Io-ref Pt Tj-opr Tstg Symbol Ratings 24 1.0 0.1 -0.3 to Vcc -0.3 to Vref -0.3 to Vcaoh -0.3 to Veoh -0.3 to +6.5 300 -200 800 1 -1.5 to 0.3 -5 1 -40 to 125 -55 to 150 Unit V A A V V V V V A A A mA V mA W C C 6, 7 Note 3 4 5
Rated voltages are with reference to the GND pin. For rated currents, inflow to the IC is indicated by (+), and outflow by (-). The transient current when driving a capacitive load. This is the rated voltage for the following pins: OUT 5. This is the rated voltage for the following pins: VREF, FB, IAC, SS, RT, CT 6. HA16178P (DILP) type: ja = 120C/W 7. HA16178FP (SOP) type: ja = 120C/W This is value mounted on glass epoxy board of 10% wiring density and 40 mm x 40 mm x 1.6 mm.
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 4 of 24
HA16178P/FP
Electrical Characteristics
(Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supply Item Start threshold Shutdown threshold UVLO hysteresis Start-up current Is temperature stability VREF Operating current Output voltage Line regulation Load regulation Oscillator Temperature stability Initial accuracy fout temperature stability fout voltage stability CT peak voltage Ramp valley voltage Soft start Current limit VAMP RT voltage Sink current Threshold voltage1 Delay to output Feedback voltage Input bias current Open loop gain High voltage Low voltage Source current Sink current Transconductance CAMP Input offset voltage Open loop gain High voltage Low voltage Source current Sink current Transconductance Note: 1. Design spec. Symbol VH VL dVUVL Is dIs/dTa Icc Vref Vref-line Vref-load dVref fout dfout/dTa fout-line Vct-H Vct-L Vrt Iss VCL1 td-CL Vfb Ifb Av-v Veoh Veol Isrc-eo Isnk-eo Gm-v Vio-ca Av-ca Vcaoh Vcaol Isrc-ca Isnk-ca Gm-c Min 9.8 8.5 1.0 140 -- 3.45 4.85 -- -- -- 58.5 -- -1.5 -- -- 1.07 15.0 -0.33 -- 2.40 -0.3 -- 5.2 -- -- -- 150 -- -- 5.2 -- -- -- 150 Typ 10.5 9.0 1.5 200 -0.3 4.5 5.00 5 5 80 65 0.1 0.5 3.6 0.65 1.25 25.0 -0.30 280 2.50 0 60 5.7 0.1 -120 120 200 (-10) 60 5.7 0.1 -90 90 200 Max 11.2 9.5 2.0 260 -- 6.45 5.15 20 20 -- 71.5 -- 1.5 4.0 -- 1.43 35.0 -0.27 500 2.60 0.3 -- 6.2 0.3 -- -- 290 0 -- 6.2 0.3 -- -- 290 Unit V V V A %/C mA V mV mV ppm/C kHz %/C % V V V A V ns V A dB V V A A A/V mV dB V V A A A/V CAO = 2.5 V * 1 CAO = 2.5 V * *
1 1
Test Conditions
VCC = 9.5 V 1 * IAC = 0 A, CL = 0 F Isource = 1 mA Isource = 1 mA, VCC = 12 V to 23 V Isource = 1 mA to 5 mA Ta = -40 to 125C * Measured pin: OUT Ta = -40 to 125C * VCC = 12 V to 18 V * 1 * SS = 2 V PFC-ON = 2 V CS = 0 to -1 V FB-EO Short Measured pin: FB * FB = 2.3 V, EO: Open FB = 2.7 V, EO: Open FB = 1.0 V, EO = 2.5 V FB = 4.0 V, EO = 2.5 V FB = 2.5 V, EO = 2.5 V * 1 *
1 1 1 1
1
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 5 of 24
HA16178P/FP (Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
IAC/ Multiplier Item IAC PIN voltage Terminal offset current Output current (PFC-ON = 2.5 V) Output current (PFC-ON = 5.5 V) PFC-CS resistance OUT Gain voltage Minimum duty cycle Maximum duty cycle Rise time Fall time Low voltage Symbol Viac Imo-offset Imo1 Imo2 Imo3 Imo4 Rmo Vpfc-gain Dmin-out Dmax-out tr-out tf-out Vol1-out Vol2-out Vol3-out High voltage Voh1-out Voh2-out Min 1.6 -136 -- -- -- -- -- (3.4) -- 90 -- -- -- -- -- 11.5 10.0 Typ 2.3 -90 -20 -60 -5 -15 3.3 (4.1) -- 95 30 30 0.05 0.5 0.03 11.9 11.0 Max 3.0 -73 -- -- -- -- -- (4.7) 0 98 100 100 0.2 2.0 0.7 -- -- Unit V A A A A A k V % % ns ns V V V V V Test Conditions IAC = 100 A IAC = 0 A, CS = 0 V 1,2 EO = 2 V, IAC = 100 A * EO = 4 V, IAC = 100 A * 1,2 EO = 2 V, IAC = 100 A *
1,2
EO = 4 V, IAC = 100 A * 1 * Gain = 0.125* CAO = 4.0 V CAO = 0 V CL = 1000 pF CL = 1000 pF Iout = 20 mA
1
1,2
Iout = 200 mA (Pulse Test) Iout = 10 mA, VCC = 5 V Iout = -20 mA Iout = -200 mA (Pulse Test)
Notes: 1. Design spec. 2. Imo1 to Imo4 defined as, Imo = (CS Terminal Current) - (Imo-offset)
CAO
IMO = K x {IAC x (VEO - 1 V)}
IAC
K
O VE
CAMP
IAC
Oscillator
VREF
3.3 k Imo 55 k
-0.3 V CLIMIT
Terminal Current
Imo-offset
CS
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 6 of 24
HA16178P/FP (Ta = 25C, VCC = 12 V, RT = 27 k, CT = 1000 pF)
Supervisor/ PG Item PFC enable voltage PFC disable voltage Input current B+ OVP set voltage B+ OVP reset voltage FB low set voltage Note: 1. dVovps = Vovps - Vref x 0.5 dVovpr = Vovpr - Vref x 0.5
Vovps FB Vfbls
Symbol Von-pfc Voff-pfc Ipfc-on dVovps dVovpr Vfbls
Min 1.62 1.48 -- 0.125 0.075 0.45
Typ 1.75 1.6 0.1 0.188 0.138 0.50
Max 1.87 1.72 1.0 0.250 0.200 0.55
Unit V V A V V V
Test Conditions Input pin: PFC-ON Input pin: PFC-ON PFC-ON = 2 V Input pin: FB * 1 Input pin: FB * Input pin: FB
1
Vovpr
Vref x 0.5
OUT
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 7 of 24
HA16178P/FP
Timing Chart
1. Start-up Timing
VCC
10.5 V (VH)
5V 4.0 V
VREF
VREF GOOD
PFC-ON
1.75 V (Von-pfc)
PFC-OFF (Internal signal)
SS CAO
Soft start
CAO SS
OUT
Normal operation
+B voltage
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 8 of 24
HA16178P/FP 2. Oscillator, Gate Driver Output
CT
CAO
Dead time (Internal signal)
OUT (Leading edge control)
3. PFC Operation ON/OFF
1.75 V (Von-pfc) 1.6 V (Voff-pfc)
PFC-ON
SS
OUT
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 9 of 24
HA16178P/FP 4. FB Supervisor
Vovps
FB
Vovpr 0.5 V (FB LOW)
B+OVP (Internal signal)
FB LOW (Internal signal)
SS
OUT
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 10 of 24
HA16178P/FP 5. PFC ON/OFF Function
Em R1 720 k R2 20 k C1 2.2 5 PFC-ON 1.75 V 1.60 V PFC ON/OFF control
Rec+
Rec-
VPFC-ON (DC) =
2 x Em R2 x R1 + R2 2 x 2 x Vac R2 = x R1 + R2 VPFC-ON (DC) x R1 + R2 x Vac = 2 x 2 R2
Vac 71.9 V 65.8 V
PFC-ON 1.75 V 1.60 V
PFC-OFF (Internal signal)
PFC ON status
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 11 of 24
HA16178P/FP
Description of Pin Functions
OUT Pin: The power MOS FET gate-drive signal is output from this pin, and takes the form of a rectangular waveform with an amplitude of VCC-GND. PGND Pin: The ground terminal for OUT driver. SGND Pin: The ground terminal for internal circuits. PFC-ON Pin: This pin is applied smoothing voltage of rectified AC voltage. When 1.75 V (typ.) or more is applied to this pin, PFC operation starts. When the voltage is 1.6 V (typ.) or lower, the PFC operation stops. VREF Pin: Temperature-compensated voltage with an accuracy of 5 V 3% is output from this pin. The pin should supply no more than 5 mA (max.) source current. This pin has no sink capabilities. CAO Pin: This pin is the current-error amplifier output, and is connected to the phase-compensation circuit of the current-error amp. The result of comparison of the voltage on this pin and the CT pin produces the pulse output from the OUT pin. CS Pin: Current detection pin. The current is controlled to be proportional to the AC voltage and the power factor is corrected. When the voltage on this pin drops to -0.3 V (typ.) or below, over current detection circuit operates, and OUT pin is stopped. RT Pin: A pin for frequency adjustment of the oscillator. CT Pin: A pin for frequency adjustment of the oscillator. IAC Pin: This pin is for detecting the input AC voltage waveform. For processing within the IC, the AC voltage waveform is converted to current information. FB Pin: This pin is the input to the voltage error amp. This pin is applied to voltage divided PFC output with resistors. The feedback loop is intended to keep 2.5 V (typ.). EO Pin: This pin is the output of the voltage error amp. This pin is connected to the phase-compensation circuit of the voltage error amp. The voltage on this pin is the input signal to the internal multiplier. SS Pin: This pin is connected to GND or VREF via a capacitor. This pin is pulled up to the VREF pin voltage until PFC operation starts. When the voltage on the PFC-ON pin has reached 1.75 V (typ.) PFC operation is start and this pin flows 25 A source current. Operation of the CAO pin is affected by that of the SS pin, the pulse width of the OUT pin is limited, and this prevents overshooting when start up. VCC Pin: IC power-supply pin. The IC starts up at 10.5 V (typ.), and stops at 9 V (typ.).
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 12 of 24
HA16178P/FP
Description of Functions
1. UVL Circuit The UVL circuit monitors the Vcc voltage. When the voltage is lower than 9.0 V, the IC is stopped. When the voltage is higher than 10.5 V, IC is started. When operation of the IC is stopped by the UVL circuit, the driver circuit output is fixed low, output of VREF is stopped, and the oscillator is stopped.
VCC
10.5 V (VH)
9 V (VL)
5V VREF 4.0 V CAO
CT
OUT
Figure 1 UVL Operation
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 13 of 24
HA16178P/FP 2. Operating Frequency The HA16178 operating frequency fosc is determined by adjusting the timing resistor Rt (the RT pin, pin 9) and the timing capacitance Ct (the CT pin, pin 10). The operating frequency is approximated by the following expression:
fosc = 1.755 x 106 (kHz) Rt (k) x Ct (pF)
When the IC is operated at high frequencies, the expression becomes less accurate due to IC internal delay time, etc. Please confirm operation the value with the actually mounted IC. The maximum operating frequency is 400 kHz. As a reference, the operating frequency data when the timing resistor and the timing capacitance are changed is shown in the below figure.
1000
Operating Frequency (kHz)
100
Timing capacitance Ct 470 pF 1000 pF 2200 pF
10
4700 pF
1 1 10 Timing Resistance (k) 100
Figure 2 Operating Frequency Characteristics
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 14 of 24
HA16178P/FP 3. Soft Start This function prevents applying excessive stress on external components and overshooting of the PFC output voltage (B + voltage) when start up. The pulse width is gradually widening from 0% duty cycle. During soft-start operation, the SS and CAO signals lower with link. The duty cycle is controlled by the CAO signal. The soft-start time can be set by an external capacity.
1.75 V CAO SS SS
PFC-ON
CAO
CT
OUT
PFC output voltage
Figure 3 Soft-Start Operation Waveform
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 15 of 24
HA16178P/FP
Main Characteristics
Standby Current vs. Power Supply Voltage Characteristics 250 Ta = 25C 200
Is (A)
150
100
50
0 0 1 2 3 4 5 6 Vcc (V) 7 8 9 10 11
Power Dissipation vs. Power Supply Voltage Characteristics 8 7.5 7 6.5
Icc (mA)
Ta = 25C CL = 1000 pF
6 5.5 5 4.5 4 3.5 10 12 14 16 Vcc (V) 18 20 22 24
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 16 of 24
HA16178P/FP
Reference Voltage Temperature Characteristics 5.2 5.15 5.1 Vcc = 12 V Iref = -1 mA
VREF (V)
5.05 5 4.95 4.9 4.85 4.8 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Frequency Temperature Characteristics 75 73 71 Vcc = 12 V RT= 27 k CT = 1000 pF
Frequency (kHz)
69 67 65 63 61 59 57 55 -40 -20 0 20 40 Ta (C) 60 80 100 120
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 17 of 24
HA16178P/FP
Start-up Voltage Temperature Characteristics 11.5 11.3 11.1 10.9
VH (V)
10.7 10.5 10.3 10.1 9.9 9.7 9.5 -40 -20 0 20 40 Ta (C) 60 80 100 120
Shutdown Voltage Temperature Characteristics 9.6
9.4
9.2
VL (V)
9
8.8
8.6
8.4 -40
-20
0
20
40 Ta (C)
60
80
100
120
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 18 of 24
HA16178P/FP
Standby Current Temperature Characteristics 280 Vcc = 9.5 V 260 240 220
Is (A)
200 180 160 140 120 -40
-20
0
20
40 Ta (C)
60
80
100
120
Operating Current Temperature Characteristics 7 6.5 6 5.5 5 4.5 4 3.5 3 -40 Vcc = 12 V CL = 0 pF
Icc (mA)
-20
0
20
40 Ta (C)
60
80
100
120
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 19 of 24
HA16178P/FP
VAMP Feedback Voltage Temperature Characteristics 2.7 2.65 2.6 2.55
Vfb (V)
Vcc = 12 V FB-EO Short
2.5 2.45 2.4 2.35 2.3 -40
-20
0
20
40 Ta (C)
60
80
100
120
EO Pin Voltage vs. CS Pin Current Characteristics 100 90 80 70
-Imo (A)
Ta = 25C Vcc = 12 V Iac = 100 A
60 50 40 30 20 10 0 0 1 2 Veo (V) 3 4 5 PFC-ON = 5.5 V PFC-ON = 2.5 V
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 20 of 24
HA16178P/FP
Vamp Frequency Characteristics
80 60 40
Ta = 25C Vcc = 12 V
200
150 100 50 0 -50 -100 -150
Gain (dB)
20 0 -20 -40 -60 -80 10E+0
100E+0
1E+3
10E+3 100E+3 Frequency f (Hz)
1E+6
-200 10E+6
Camp Frequency Characteristics 80 60 40 Ta = 25C Vcc = 12 V 200 150 100 50
Gain (dB)
20 0 -20 -40 -60 -80 10E+0
0
-50 -100 -150 -200 10E+6
100E+0
1E+3
10E+3 100E+3 Frequency f (Hz)
1E+6
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 21 of 24
Phase (deg.)
Phase (deg.)
HA16178P/FP
Precautions on Usage
1. CS Pin The CS pin is used to for detection in PFC control led current. When power supply is started up, the voltage drop of inrush current must not exceed the maximum rated value of the CS pin. 2. VREF Pin For stabilization, be sure to connect a capacitor between the pin and ground. It possible to occur overshoot of VREF by connected capacitance. The degree of the overshoot will depend on the value of the connected capacitor. Pay particular attention to this point if you intend to use the VREF pin voltage as reference voltage for an external circuit.
Vref Overshoot
Vref Peak Voltage (V)
7 6.5 6 5.5 5 0.01
0.1 Cref (F)
1
Figure 4 Overshoot on the VREF Pin vs. Capacitance 3. PFC-ON Pin In design of worldwide power supply, it is possible that calculated voltage exceed maximum rated voltage of PFC-ON pin. Actually, as a clamp circuit is included in the PFC-ON pin, the voltage is clamped however, clamp current must not exceed 300 A. 4. OUT Pin Undershooting or overshooting may occur due to the wiring of the OUT pin. These may bring to malfunctions of the IC. In such a case, prevent the undershooting or overshooting by using a Schottky barrier diode, etc.
5. Pattern Layout In designing the pattern layout, pay as much attention as is possible to the following points. (1) Place the stabilizing capacitor for the VREF pin as close to the IC as possible, and keep the wiring short. (2) Place the timing resistor of the RT pin as close to the IC as possible, and keep the wiring short. (3) Place the phase compensation circuit for the CAO pin as close to the IC as possible, and keep the wiring short. (4) Place the timing capacitor for the CT pin as close to the IC as possible, and keep the wiring short. (5) Place the stabilizing capacitor for the VCC pin as close to the IC as possible, and keep the wiring short. (6) Place the IC pins and their wiring as far from high-voltage switching lines (particularly the drain voltage for the power MOS FET) as possible and in general design the wiring to minimize switching noise. (7) It is probable that stability of operation is achieved by inputting signals via filters to pins with input functions. Note, however, that such filter circuits can affect the bias conditions for pins that have both input and output functions. 6. About NC Terminal NC terminal uses open.
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 22 of 24
HA16178P/FP
System Diagram
Rec+ B+
B+ OUT (385 V dc)
T1 Q1
470 (450 V)
680 k
To FB
680 k
Rec-
From OUT
from auxiliary
24 V 4.7
VRB1
GND
VCC
16
5 V Internal Bias
H
10.5 V
VREF
5 V VREF Generator
27.5 V
L
UVLO
9.0 V
6
VREF In GOOD Out
VREF GOOD
0.1
27 k
RT
9
770 ns 15.4 s 0.65 V 3.6 V
PFC-DT
RAMP
CT
10
1000 p
UVL
65 kHz
R S
Q Q
Gate Driver 1.0 A (PEAK)
To Q1 gate
VREF CAO 3.3 n 30 k
Oscillator
7
1
OUT
R S
Q Q
470 p
3M
IMO = K x {IAC x (VEO - 1 V)}
VREF
SS
IAC
12
IAC
O
CAMP
IMO
1.75 M
1000 p
VE
VREF
K
55 k 3.3 k
100
CS
8
CLIMIT
0.016 (5 W)
0.01
Gain Select
K = 0.20
-0.30 V
820 k
EO
14
2.5 V
Gain Selector
VREF
K = 0.05
VREF
4.7
15
33 n
FB
13
From VRB1 (B+ monitor1)
720 k
SS
VAMP
2.688 V 2.638 V
B+OVP 25 A
PGND
2
PFC-ON
5
2.2 20 k
0.1
0.50 V
FB LOW
PFC-OFF
SGND
1.75 V 1.60 V
3
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 23 of 24
HA16178P/FP
Package Dimensions
JEITA Package Code P-DIP16-6.3x19.2-2.54 RENESAS Code PRDP0016AE-B Previous Code DP-16FV MASS[Typ.] 1.05g
D
16
9
1 0.89 b3
8
Z
A1
A
E
Reference Symbol
Dimension in Millimeters
Min
e
bp
e1
c
( Ni/Pd/Au plating )
e1 D E A A1 bp b3 c e Z L
Nom Max 7.62 19.2 20.32 6.3 7.4 5.06
L
0.51 0.40 0.48 0.56 1.30 0.19 0.25 0.31 0 15 2.29 2.54 2.79 1.12 2.54
JEITA Package Code P-SOP16-5.5x10.06-1.27
RENESAS Code PRSP0016DH-B
Previous Code FP-16DAV
MASS[Typ.] 0.24g
*1
D F 9
16
NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
bp
HE
E
Index mark
*2
Terminal cross section ( Ni/Pd/Au plating )
1 Z e
*3
8 bp x M L1
Reference Symbol
c
Dimension in Millimeters
A1
y
L
Detail F
D E A2 A1 A bp b1 c c1 HE e x y Z L L1
Min Nom Max 10.06 10.5 5.50 0.00 0.10 0.20 2.20 0.34 0.40 0.46 0.15 0.20 0.25 0 8 7.50 7.80 8.00 1.27 0.12 0.15 0.80 0.50 0.70 0.90 1.15
REJ03D0903-0100 Rev.1.00 Jun 12, 2007 Page 24 of 24
A
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Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.
RENESAS SALES OFFICES
Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K. Tel: <44> (1628) 585-100, Fax: <44> (1628) 585-900 Renesas Technology (Shanghai) Co., Ltd. Unit 204, 205, AZIACenter, No.1233 Lujiazui Ring Rd, Pudong District, Shanghai, China 200120 Tel: <86> (21) 5877-1818, Fax: <86> (21) 6887-7898 Renesas Technology Hong Kong Ltd. 7th Floor, North Tower, World Finance Centre, Harbour City, 1 Canton Road, Tsimshatsui, Kowloon, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2730-6071 Renesas Technology Taiwan Co., Ltd. 10th Floor, No.99, Fushing North Road, Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology Singapore Pte. Ltd. 1 Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 Renesas Technology Korea Co., Ltd. Kukje Center Bldg. 18th Fl., 191, 2-ka, Hangang-ro, Yongsan-ku, Seoul 140-702, Korea Tel: <82> (2) 796-3115, Fax: <82> (2) 796-2145
http://www.renesas.com
Renesas Technology Malaysia Sdn. Bhd Unit 906, Block B, Menara Amcorp, Amcorp Trade Centre, No.18, Jalan Persiaran Barat, 46050 Petaling Jaya, Selangor Darul Ehsan, Malaysia Tel: <603> 7955-9390, Fax: <603> 7955-9510
(c) 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
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